Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Clock bindings for Axis ARTPEC-6 chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The bindings are based on the clock provider binding in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Documentation/devicetree/bindings/clock/clock-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) External clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) ----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) There are two external inputs to the main clock controller which should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) provided using the common clock bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - "sys_refclk": External 50 Mhz oscillator (required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - "i2s_refclk": Alternate audio reference clock (optional).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Main clock controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - #clock-cells: Should be <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)   See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - compatible: Should be "axis,artpec6-clkctrl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - reg: Must contain the base address and length of the system controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - clocks:  Must contain a phandle entry for each clock in clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - clock-names: Must include the external oscillator ("sys_refclk"). Optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   ones are the audio reference clock ("i2s_refclk") and the audio fractional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)   dividers ("frac_clk0" and "frac_clk1").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ext_clk: ext_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	clock-frequency = <50000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) clkctrl: clkctrl@f8000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	compatible = "axis,artpec6-clkctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	reg = <0xf8000000 0x48>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	clocks = <&ext_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	clock-names = "sys_refclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };