Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Time Base Generator Clock bindings for Marvell Armada 37xx SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Marvell Armada 37xx SoCs provde Time Base Generator clocks which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) used as parent clocks for the peripheral clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) The TBG clock consumer should specify the desired clock by having the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) clock ID in its "clocks" phandle cell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) The following is a list of provided IDs and clock names on Armada 3700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  0 = TBG A P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  1 = TBG B P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  2 = TBG A S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  3 = TBG B S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - compatible : shall be "marvell,armada-3700-tbg-clock"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - reg : must be the register address of North Bridge PLL register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - #clock-cells : from common clock binding; shall be set to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) tbg: tbg@13200 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	compatible = "marvell,armada-3700-tbg-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	reg = <0x13200 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	clocks = <&xtalclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };