Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Peripheral Clock bindings for Marvell Armada 37xx SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Marvell Armada 37xx SoCs provide peripheral clocks which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) used as clock source for the peripheral of the SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) There are two different blocks associated to north bridge and south
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) The peripheral clock consumer should specify the desired clock by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) having the clock ID in its "clocks" phandle cell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) The following is a list of provided IDs for Armada 3700 North bridge clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ID	Clock name	Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) -----------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 0	mmc		MMC controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 1	sata_host	Sata Host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 2	sec_at		Security AT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 3	sac_dap		Security DAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 4	tsecm		Security Engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 5	setm_tmx	Serial Embedded Trace Module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 6	avs		Adaptive Voltage Scaling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 7	sqf		SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 8	pwm		PWM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 9	i2c_2		I2C 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 10	i2c_1		I2C 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 11	ddr_phy		DDR PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 12	ddr_fclk	DDR F clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 13	trace		Trace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 14	counter		Counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 15	eip97		EIP 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 16	cpu		CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) The following is a list of provided IDs for Armada 3700 South bridge clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ID	Clock name	Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) -----------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 0	gbe-50		50 MHz parent clock for Gigabit Ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 1	gbe-core	parent clock for Gigabit Ethernet core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 2	gbe-125		125 MHz parent clock for Gigabit Ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 3	gbe1-50		50 MHz clock for Gigabit Ethernet port 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 4	gbe0-50		50 MHz clock for Gigabit Ethernet port 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 5	gbe1-125	125 MHz clock for Gigabit Ethernet port 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 6	gbe0-125	125 MHz clock for Gigabit Ethernet port 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 7	gbe1-core	Gigabit Ethernet core port 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 8	gbe0-core	Gigabit Ethernet core port 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 9	gbe-bm		Gigabit Ethernet Buffer Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 10	sdio		SDIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 11	usb32-sub2-sys	USB 2 clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 12	usb32-ss-sys	USB 3 clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 13	pcie		PCIe controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - compatible : shall be "marvell,armada-3700-periph-clock-nb" for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)   north bridge block, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)   "marvell,armada-3700-periph-clock-sb" for the south bridge block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) - reg : must be the register address of North/South Bridge Clock register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) - #clock-cells : from common clock binding; shall be set to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) - clocks : list of the parent clock phandle in the following order:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)   TBG-A P, TBG-B P, TBG-A S, TBG-B S and finally the xtal clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) nb_perih_clk: nb-periph-clk@13000{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	compatible = "marvell,armada-3700-periph-clock-nb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	reg = <0x13000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	<&tbg 3>, <&xtalclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };