Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) External Memory Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) -------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) The emifa node describes a simple external bus controller found on some C6X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) SoCs. This interface provides external busses with a number of chip selects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - compatible: must be "ti,c64x+emifa", "simple-bus"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - reg: register area base and size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - #address-cells: must be 2 (chip-select + offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - #size-cells: must be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - ranges: mapping from EMIFA space to parent space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - ti,dscr-dev-enable: Device ID if EMIF is enabled/disabled from DSCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - ti,emifa-burst-priority:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)       Number of memory transfers after which the EMIF will elevate the priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)       of the oldest command in the command FIFO. Setting this field to 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)       disables this feature, thereby allowing old commands to stay in the FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)       indefinitely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - ti,emifa-ce-config:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)       Configuration values for each of the supported chip selects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	emifa@70000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		compatible = "ti,c64x+emifa", "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		#address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		reg = <0x70000000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		ranges = <0x2 0x0 0xa0000000 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		          0x3 0x0 0xb0000000 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			  0x4 0x0 0xc0000000 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			  0x5 0x0 0xD0000000 0x10000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		ti,dscr-dev-enable = <13>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		ti,emifa-burst-priority = <255>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		ti,emifa-ce-config = <0x00240120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 				      0x00240120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 				      0x00240122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 				      0x00240122>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		flash@3,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 			#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 			compatible = "cfi-flash";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			reg = <0x3 0x0 0x400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			bank-width = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			device-width = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 			partition@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 				reg = <0x0 0x400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 				label = "NOR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) This shows a flash chip attached to chip select 3.