^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Device State Configuration Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) ------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) TI C6X SoCs contain a region of miscellaneous registers which provide various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) function for SoC control or status. Details vary considerably among from SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) to SoC with no two being alike.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) In general, the Device State Configuration Registers (DSCR) will provide one or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) more configuration registers often protected by a lock register where one or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) more key values must be written to a lock register in order to unlock the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) configuration register for writes. These configuration register may be used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) enable (and disable in some cases) SoC pin drivers, select peripheral clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) sources (internal or pin), etc. In some cases, a configuration register is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) write once or the individual bits are write once. In addition to device config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) the DSCR block may provide registers which are used to reset peripherals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) provide device ID information, provide ethernet MAC addresses, as well as other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) miscellaneous functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) For device state control (enable/disable), each device control is assigned an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) id which is used by individual device drivers to control the state as needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - compatible: must be "ti,c64x+dscr"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - reg: register area base and size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) NOTE: These are optional in that not all SoCs will have all properties. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) SoCs which do support a given property, leaving the property out of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) device tree will result in reduced functionality or possibly driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - ti,dscr-devstat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) offset of the devstat register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - ti,dscr-silicon-rev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) offset, start bit, and bitsize of silicon revision field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - ti,dscr-rmii-resets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) offset and bitmask of RMII reset field. May have multiple tuples if more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) than one ethernet port is available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - ti,dscr-locked-regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) possibly multiple tuples describing registers which are write protected by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) a lock register. Each tuple consists of the register offset, lock register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) offsset, and the key value used to unlock the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - ti,dscr-kick-regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) offset and key values of two "kick" registers used to write protect other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) registers in DSCR. On SoCs using kick registers, the first key must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) written to the first kick register and the second key must be written to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) the second register before other registers in the area are write-enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - ti,dscr-mac-fuse-regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MAC addresses are contained in two registers. Each element of a MAC address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) is contained in a single byte. This property has two tuples. Each tuple has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) a register offset and four cells representing bytes in the register from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) most significant to least. The value of these four cells is the MAC byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) index (1-6) of the byte within the register. A value of 0 means the byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) is unused in the MAC address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) - ti,dscr-devstate-ctl-regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) This property describes the bitfields used to control the state of devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) Each tuple describes a range of identical bitfields used to control one or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) more devices (one bitfield per device). The layout of each tuple is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) start_id num_ids reg enable disable start_bit nbits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) Where:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) start_id is device id for the first device control in the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) num_ids is the number of device controls in the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) reg is the offset of the register holding the control bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) enable is the value to enable a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) disable is the value to disable a device (0xffffffff if cannot disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) start_bit is the bit number of the first bit in the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) nbits is the number of bits per device control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) - ti,dscr-devstate-stat-regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) This property describes the bitfields used to provide device state status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) for device states controlled by the DSCR. Each tuple describes a range of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) identical bitfields used to provide status for one or more devices (one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) bitfield per device). The layout of each tuple is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) start_id num_ids reg enable disable start_bit nbits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) Where:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) start_id is device id for the first device status in the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) num_ids is the number of devices covered by the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) reg is the offset of the register holding the status bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) enable is the value indicating device is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) disable is the value indicating device is disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) start_bit is the bit number of the first bit in the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) nbits is the number of bits per device status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) - ti,dscr-privperm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) Offset and default value for register used to set access privilege for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) some SoC devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) device-state-config-regs@2a80000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) compatible = "ti,c64x+dscr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) reg = <0x02a80000 0x41000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ti,dscr-devstat = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ti,dscr-silicon-rev = <8 28 0xf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ti,dscr-rmii-resets = <0x40020 0x00040000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ti,dscr-devstate-ctl-regs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) <0 12 0x40008 1 0 0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 12 1 0x40008 3 0 30 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 13 2 0x4002c 1 0xffffffff 0 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ti,dscr-devstate-stat-regs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) <0 10 0x40014 1 0 0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 10 2 0x40018 1 0 0 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0x704 5 6 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ti,dscr-kick-regs = <0x38 0x83E70B13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 0x3c 0x95A4F1E0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
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