^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Texas Instruments sysc interconnect target module wrapper binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Texas Instruments SoCs can have a generic interconnect target module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) hardware for devices connected to various interconnects such as L3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) is mostly used for interaction between module and PRCM. It participates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) in the OCP Disconnect Protocol but other than that is mostly independent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) of the interconnect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Each interconnect target module can have one or more devices connected to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) it. There is a set of control registers for managing interconnect target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) module clocks, idle modes and interconnect level resets for the module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) These control registers are sprinkled into the unused register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) space of the first child device IP block managed by the interconnect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) target module and typically are named REVISION, SYSCONFIG and SYSSTATUS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Required standard properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - compatible shall be one of the following generic types:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) "ti,sysc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) "ti,sysc-omap2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) "ti,sysc-omap4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) "ti,sysc-omap4-simple"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) or one of the following derivative types for hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) needing special workarounds:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) "ti,sysc-omap2-timer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) "ti,sysc-omap4-timer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) "ti,sysc-omap3430-sr"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) "ti,sysc-omap3630-sr"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "ti,sysc-omap4-sr"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "ti,sysc-omap3-sham"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "ti,sysc-omap-aes"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) "ti,sysc-mcasp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) "ti,sysc-dra7-mcasp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) "ti,sysc-usb-host-fs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "ti,sysc-dra7-mcan"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "ti,sysc-pruss"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - reg shall have register areas implemented for the interconnect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) target module in question such as revision, sysc and syss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - reg-names shall contain the register names implemented for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) interconnect target module in question such as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "rev, "sysc", and "syss"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) - ranges shall contain the interconnect target module IO range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) available for one or more child device IP blocks managed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) by the interconnect target module, the ranges may include
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) multiple ranges such as device L4 range for control and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) parent L3 range for DMA access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) - ti,sysc-mask shall contain mask of supported register bits for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SYSCONFIG register as documented in the Technical Reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) Manual (TRM) for the interconnect target module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) - ti,sysc-midle list of master idle modes supported by the interconnect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) target module as documented in the TRM for SYSCONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) register MIDLEMODE bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) - ti,sysc-sidle list of slave idle modes supported by the interconnect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) target module as documented in the TRM for SYSCONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) register SIDLEMODE bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) - ti,sysc-delay-us delay needed after OCP softreset before accssing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) SYSCONFIG register again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) - ti,syss-mask optional mask of reset done status bits as described in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) TRM for SYSSTATUS registers, typically 1 with some devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) having separate reset done bits for children like OHCI and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) EHCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) - clocks clock specifier for each name in the clock-names as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) specified in the binding documentation for ti-clkctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) typically available for all interconnect targets on TI SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) based on omap4 except if it's read-only register in hwauto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mode as for example omap4 L4_CFG_CLKCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) - clock-names should contain at least "fck", and optionally also "ick"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) depending on the SoC and the interconnect target module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) some interconnect target modules also need additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) optional clocks that can be specified as listed in TRM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) for the related CLKCTRL register bits 8 to 15 such as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "dbclk" or "clk32k" depending on their role
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) - ti,hwmods optional TI interconnect module name to use legacy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) hwmod platform data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) - ti,no-reset-on-init interconnect target module should not be reset at init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) - ti,no-idle-on-init interconnect target module should not be idled at init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) - ti,no-idle interconnect target module should not be idled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) Example: Single instance of MUSB controller on omap4 using interconnect ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) compatible = "ti,sysc-omap2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ti,hwmods = "usb_otg_hs";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) reg = <0x2b400 0x4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) <0x2b404 0x4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) <0x2b408 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) reg-names = "rev", "sysc", "syss";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) clock-names = "fck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SYSC_OMAP2_SOFTRESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SYSC_OMAP2_AUTOIDLE)>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ti,sysc-midle = <SYSC_IDLE_FORCE>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) <SYSC_IDLE_NO>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) <SYSC_IDLE_SMART>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ti,sysc-sidle = <SYSC_IDLE_FORCE>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) <SYSC_IDLE_NO>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) <SYSC_IDLE_SMART>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) <SYSC_IDLE_SMART_WKUP>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ti,syss-mask = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ranges = <0 0x2b000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) usb_otg_hs: otg@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) compatible = "ti,omap4-musb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) reg = <0x0 0x7ff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) usb-phy = <&usb2_phy>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) Note that other SoCs, such as am335x can have multiple child devices. On am335x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) instance as children of a single interconnect target module.
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