Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) * Marvell MBus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) - compatible:	 Should be set to one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 		 marvell,armada370-mbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 		 marvell,armadaxp-mbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 		 marvell,armada375-mbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 		 marvell,armada380-mbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 		 marvell,kirkwood-mbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 		 marvell,dove-mbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 		 marvell,orion5x-88f5281-mbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 		 marvell,orion5x-88f5182-mbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 		 marvell,orion5x-88f5181-mbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 		 marvell,orion5x-88f6183-mbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 		 marvell,mv78xx0-mbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) - address-cells: Must be '2'. The first cell for the MBus ID encoding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)                  the second cell for the address offset within the window.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) - size-cells:    Must be '1'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) - ranges:        Must be set up to provide a proper translation for each child.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	         See the examples below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) - controller:    Contains a single phandle referring to the MBus controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)                  node. This allows to specify the node that contains the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		 registers that control the MBus, which is typically contained
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		 within the internal register window (see below).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) - pcie-mem-aperture:	This optional property contains the aperture for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 			the memory region of the PCIe driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 			If it's defined, it must encode the base address and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 			size for the address decoding windows allocated for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 			the PCIe memory region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) - pcie-io-aperture:	Just as explained for the above property, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 			optional property contains the aperture for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 			I/O region of the PCIe driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) * Marvell MBus controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) - compatible:	Should be set to "marvell,mbus-controller".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) - reg:          Device's register space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		Two or three entries are expected (see the examples below):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		the first one controls the devices decoding window,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		the second one controls the SDRAM decoding window and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		the third controls the MBus bridge (only with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		marvell,armada370-mbus and marvell,armadaxp-mbus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		compatible strings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		compatible = "marvell,armada370-mbus", "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		#address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		controller = <&mbusc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		pcie-mem-aperture = <0xe0000000 0x8000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		pcie-io-aperture  = <0xe8000000 0x100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		internal-regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			compatible = "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			mbusc: mbus-controller@20000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 				compatible = "marvell,mbus-controller";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 				reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			/* more children ...*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) ** MBus address decoding window specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) The MBus children address space is comprised of two cells: the first one for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) the window ID and the second one for the offset within the window.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) In order to allow to describe valid and non-valid window entries, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) following encoding is used:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)   0xSIAA0000 0x00oooooo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) Where:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)   S = 0x0 for a MBus valid window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)   S = 0xf for a non-valid window (see below)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) If S = 0x0, then:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)    I = 4-bit window target ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)   AA = windpw attribute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) If S = 0xf, then:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)    I = don't care
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)    AA = 1 for internal register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) Following the above encoding, for each ranges entry for a MBus valid window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) (S = 0x0), an address decoding window is allocated. On the other side,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) entries for translation that do not correspond to valid windows (S = 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) are skipped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		compatible = "marvell,armada370-mbus", "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		#address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		controller = <&mbusc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		ranges = <0xf0010000 0 0 0xd0000000 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			  0x01e00000 0 0 0xfff00000 0x100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		bootrom {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			compatible = "marvell,bootrom";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			reg = <0x01e00000 0 0x100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		/* other children */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		internal-regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			compatible = "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			ranges = <0 0xf0010000 0 0x100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			mbusc: mbus-controller@20000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 				compatible = "marvell,mbus-controller";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			/* more children ...*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) In the shown example, the translation entry in the 'ranges' property is what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) makes the MBus driver create a static decoding window for the corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) given child device. Note that the binding does not require child nodes to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) present. Of course, child nodes are needed to probe the devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) Since each window is identified by its target ID and attribute ID there's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) a special macro that can be use to simplify the translation entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) Using this macro, the above example would be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		compatible = "marvell,armada370-mbus", "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		#address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		controller = <&mbusc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		ranges = < MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			   MBUS_ID(0x01, 0xe0) 0 0 0xfff00000 0x100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		bootrom {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			compatible = "marvell,bootrom";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		/* other children */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		internal-regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			compatible = "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			mbusc: mbus-controller@20000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 				compatible = "marvell,mbus-controller";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 				reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			/* other children */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ** About the window base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) Remember the MBus controller allows a great deal of flexibility for choosing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) the decoding window base address. When planning the device tree layout it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) possible to choose any address as the base address, provided of course there's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) a region large enough available, and with the required alignment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) Yet in other words: there's nothing preventing us from setting a base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) of 0xf0000000, or 0xd0000000 for the NOR device shown above, if such region is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ** Window allocation policy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) The mbus-node ranges property defines a set of mbus windows that are expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) to be set by the operating system and that are guaranteed to be free of overlaps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) with one another or with the system memory ranges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) Each entry in the property refers to exactly one window. If the operating system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) chooses to use a different set of mbus windows, it must ensure that any address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) translations performed from downstream devices are adapted accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) The operating system may insert additional mbus windows that do not conflict
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) with the ones listed in the ranges, e.g. for mapping PCIe devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) As a special case, the internal register window must be set up by the boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) loader at the address listed in the ranges property, since access to that region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) is needed to set up the other windows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ** Example
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) See the example below, where a more complete device tree is shown:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		compatible = "marvell,armadaxp-mbus", "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		controller = <&mbusc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000   /* internal-regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		bootrom {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			compatible = "marvell,bootrom";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		devbus-bootcs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			/* NOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			nor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 				compatible = "cfi-flash";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 				reg = <0 0x8000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 				bank-width = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		pcie-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			compatible = "marvell,armada-xp-pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			device_type = "pci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			#address-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			#size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			ranges =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 				0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 				0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 				0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				0x81000800 0 0          MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			pcie@1,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 				/* Port 0, Lane 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		internal-regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			compatible = "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			mbusc: mbus-controller@20000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 				reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			interrupt-controller@20000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			      reg = <0x20a00 0x2d0>, <0x21070 0x58>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	};