^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Device tree bindings for i.MX Wireless External Interface Module (WEIM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The term "wireless" does not imply that the WEIM is literally an interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) without wires. It simply means that this module was originally designed for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) wireless and mobile applications that use low-power technology.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) The actual devices are instantiated from the child nodes of a WEIM node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - compatible: Should contain one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "fsl,imx1-weim"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "fsl,imx27-weim"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "fsl,imx51-weim"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "fsl,imx50-weim"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) "fsl,imx6q-weim"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - reg: A resource specifier for the register space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) (see the example below)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - clocks: the clock, see the example below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - #address-cells: Must be set to 2 to allow memory address translation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - #size-cells: Must be set to 1 to allow CS address passing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - ranges: Must be set up to reflect the memory layout with four
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) integer values for each chip-select line in use:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) <cs-number> 0 <physical address of mapping> <size>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) devices, it should be the phandle to the system General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Purpose Register controller that contains WEIM CS GPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) should be set up as one of the following 4 possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) values depending on the CS space configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ---------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 05 128M 0M 0M 0M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 033 64M 64M 0M 0M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 0113 64M 32M 32M 0M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 01111 32M 32M 32M 32M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) In case that the property is absent, the reset value or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) what bootloader sets up in IOMUXC_GPR1[11:0] will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - fsl,burst-clk-enable For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) devices, the presence of this property indicates that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) the weim bus should operate in Burst Clock Mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Timing property for child nodes. It is mandatory, not optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - fsl,weim-cs-timing: The timing array, contains timing values for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) child node. We get the CS indexes from the address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ranges in the child node's "reg" property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) The number of registers depends on the selected chip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) registers: CSxU, CSxL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) there are three registers: CSCRxU, CSCRxL, CSCRxA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) For i.MX50, i.MX53 ("fsl,imx50-weim"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) i.MX51 ("fsl,imx51-weim") and i.MX6Q ("fsl,imx6q-weim")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) there are six registers: CSxGCR1, CSxGCR2, CSxRCR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) CSxRCR2, CSxWCR1, CSxWCR2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) weim: weim@21b8000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) compatible = "fsl,imx6q-weim";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) reg = <0x021b8000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) clocks = <&clks 196>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ranges = <0 0 0x08000000 0x08000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) fsl,weim-cs-gpr = <&gpr>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) nor@0,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) compatible = "cfi-flash";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) reg = <0 0 0x02000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) bank-width = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 0x0000c000 0x1404a38e 0x00000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) Example for an imx6q-based board, a multi-chipselect device connected to WEIM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) In this case, both chip select 0 and 1 will be configured with the same timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) array values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) weim: weim@21b8000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) compatible = "fsl,imx6q-weim";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) reg = <0x021b8000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) clocks = <&clks 196>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ranges = <0 0 0x08000000 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 1 0 0x0a000000 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 2 0 0x0c000000 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 3 0 0x0e000000 0x02000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) fsl,weim-cs-gpr = <&gpr>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) acme@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) compatible = "acme,whatever";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) reg = <0 0 0x100>, <0 0x400000 0x800>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) <1 0x400000 0x800>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 0x00000000 0xa0000240 0x00000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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