Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Freescale Reference Board Bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This document describes device tree bindings for various devices that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) exist on some Freescale reference boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) * Board Control and Status (BCSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  - compatible : Should be "fsl,<board>-bcsr"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  - reg : Offset and length of the register set for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	bcsr@f8000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		compatible = "fsl,mpc8360mds-bcsr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		reg = <f8000000 8000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Freescale on-board FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) This is the memory-mapped registers for on board FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - compatible: should be a board-specific string followed by a string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)   indicating the type of FPGA.  Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	"fsl,<board>-fpga", "fsl,fpga-pixis", or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	"fsl,<board>-fpga", "fsl,fpga-qixis"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - reg: should contain the address and the length of the FPGA register set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - interrupts: should specify event (wakeup) IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Example (P1022DS):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	 board-control@3,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		 compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		 reg = <3 0 0x30>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		 interrupt-parent = <&mpic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		 interrupts = <8 8 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Example (LS2080A-RDB):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)         cpld@3,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)                 compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)                 reg = <0x3 0 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)         };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Freescale on-board FPGA connected on I2C bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) Some Freescale boards like BSC9132QDS have on board FPGA connected on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) the i2c bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) - compatible: Should be a board-specific string followed by a string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)   indicating the type of FPGA.  Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	"fsl,<board>-fpga", "fsl,fpga-qixis-i2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) - reg: Should contain the address of the FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	fpga: fpga@66 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		reg = <0x66>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Freescale on-board CPLD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) Some Freescale boards like T1040RDB have an on board CPLD connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) - compatible: Should be a board-specific string like "fsl,<board>-cpld"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)   Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	"fsl,t1040rdb-cpld", "fsl,t1042rdb-cpld", "fsl,t1042rdb_pi-cpld"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) - reg: should describe CPLD registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	cpld@3,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 		compatible = "fsl,t1040rdb-cpld";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 		reg = <3 0 0x300>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	};