Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * APM X-Gene 6.0 Gb/s SATA host controller nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) SATA host controller nodes are defined to describe on-chip Serial ATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) controllers. Each SATA controller (pair of ports) have its own node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - compatible		: Shall contain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)   * "apm,xgene-ahci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg			: First memory resource shall be the AHCI memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 			  resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 			  Second memory resource shall be the host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 			  core memory resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 			  Third memory resource shall be the host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 			  diagnostic memory resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 			  4th memory resource shall be the host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 			  AXI memory resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 			  5th optional memory resource shall be the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 			  controller MUX memory resource if required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - interrupts		: Interrupt-specifier for SATA host controller IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - clocks		: Reference to the clock entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - phys			: A list of phandles + phy-specifiers, one for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 			  entry in phy-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - phy-names		: Should contain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   * "sata-phy" for the SATA 6.0Gbps PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - dma-coherent		: Present if dma operations are coherent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - status		: Shall be "ok" if enabled or "disabled" if disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 			  Default is "ok".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		sataclk: sataclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 			compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 			clock-frequency = <100000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			clock-output-names = "sataclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		phy2: phy@1f22a000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			compatible = "apm,xgene-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			reg = <0x0 0x1f22a000 0x0 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 			#phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		phy3: phy@1f23a000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			compatible = "apm,xgene-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			reg = <0x0 0x1f23a000 0x0 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			#phy-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		sata2: sata@1a400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			compatible = "apm,xgene-ahci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			reg = <0x0 0x1a400000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			      <0x0 0x1f220000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 			      <0x0 0x1f22d000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 			      <0x0 0x1f22e000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 			      <0x0 0x1f227000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			interrupts = <0x0 0x87 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 			dma-coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 			clocks = <&sataclk 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 			phys = <&phy2 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 			phy-names = "sata-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		sata3: sata@1a800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 			compatible = "apm,xgene-ahci-pcie";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 			reg = <0x0 0x1a800000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 			      <0x0 0x1f230000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 			      <0x0 0x1f23d000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 			      <0x0 0x1f23e000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 			      <0x0 0x1f237000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 			interrupts = <0x0 0x88 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 			dma-coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 			clocks = <&sataclk 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 			phys = <&phy3 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 			phy-names = "sata-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 		};