^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) STMicroelectronics STi SATA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This binding describes a SATA device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - compatible : Must be "st,ahci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - reg : Physical base addresses and length of register sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - interrupts : Interrupt associated with the SATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - interrupt-names : Associated name must be; "hostc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - clocks : The phandle for the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - clock-names : Associated name must be; "ahci_clk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - phys : The phandle for the PHY port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - phy-names : Associated name must be; "ahci_phy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - resets : The power-down, soft-reset and power-reset lines of SATA IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - reset-names : Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Example for stih407 family silicon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) sata0: sata@9b20000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) compatible = "st,ahci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) reg = <0x9b20000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) interrupt-names = "hostc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) phys = <&phy_port0 PHY_TYPE_SATA>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) phy-names = "ahci_phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) resets = <&powerdown STIH407_SATA0_POWERDOWN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) <&softreset STIH407_SATA0_SOFTRESET>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) <&softreset STIH407_SATA0_PWR_SOFTRESET>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) clock-names = "ahci_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };