Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) MediaTek Serial ATA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  - compatible	   : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 		     When using "mediatek,mtk-ahci" compatible strings, you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 		     need SoC specific ones in addition, one of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 		     - "mediatek,mt7622-ahci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  - reg		   : Physical base addresses and length of register sets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  - interrupts	   : Interrupt associated with the SATA device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  - interrupt-names : Associated name must be: "hostc".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  - clocks	   : A list of phandle and clock specifier pairs, one for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 		     entry in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  - clock-names	   : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  - phys		   : A phandle and PHY specifier pair for the PHY port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  - phy-names	   : Associated name must be: "sata-phy".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  - ports-implemented : See ./ahci-platform.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  - power-domains   : A phandle and power domain specifier pair to the power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		     domain which is responsible for collapsing and restoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		     power to the peripheral.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  - resets	   : Must contain an entry for each entry in reset-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		     See ../reset/reset.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  - reset-names	   : Associated names must be: "axi", "sw", "reg".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  - mediatek,phy-mode : A phandle to the system controller, used to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		       SATA function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	sata: sata@1a200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		compatible = "mediatek,mt7622-ahci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			     "mediatek,mtk-ahci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		reg = <0 0x1a200000 0 0x1100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		interrupt-names = "hostc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		clocks = <&pciesys CLK_SATA_AHB_EN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 			 <&pciesys CLK_SATA_AXI_EN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			 <&pciesys CLK_SATA_ASIC_EN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			 <&pciesys CLK_SATA_RBC_EN>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			 <&pciesys CLK_SATA_PM_EN>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		clock-names = "ahb", "axi", "asic", "rbc", "pm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		phys = <&u3port1 PHY_TYPE_SATA>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		phy-names = "sata-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		ports-implemented = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			 <&pciesys MT7622_SATA_PHY_SW_RST>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			 <&pciesys MT7622_SATA_PHY_REG_RST>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		reset-names = "axi", "sw", "reg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		mediatek,phy-mode = <&pciesys>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	};