Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) # Copyright 2021, Arm Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $id: "http://devicetree.org/schemas/arm/trbe.yaml#"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) $schema: "http://devicetree.org/meta-schemas/core.yaml#"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) title: ARM Trace Buffer Extensions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   - Anshuman Khandual <anshuman.khandual@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   Arm Trace Buffer Extension (TRBE) is a per CPU component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   for storing trace generated on the CPU to memory. It is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   accessed via CPU system registers. The software can verify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   if it is permitted to use the component by checking the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   TRBIDR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   $nodename:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)     const: "trbe"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)       - const: arm,trace-buffer-extension
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)     description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)        Exactly 1 PPI must be listed. For heterogeneous systems where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)        TRBE is only supported on a subset of the CPUs, please consult
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)        the arm,gic-v3 binding for details on describing a PPI partition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)   - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)   - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)    #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)    trbe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)      compatible = "arm,trace-buffer-extension";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)      interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)    };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ...