^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Synaptics SoC Device Tree Bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) According to https://www.synaptics.com/company/news/conexant-marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Synaptics has acquired the Multimedia Solutions Business of Marvell, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) berlin SoCs are now Synaptics' SoCs now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) ---------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Work in progress statement:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Device tree files and bindings applying to Marvell Berlin SoCs and boards are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) considered "unstable". Any Marvell Berlin device tree binding may change at any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) time. Be sure to use a device tree binary and a kernel image generated from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) same source tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) stable binding/ABI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ---------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Boards with the Synaptics AS370 SoC shall have the following properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Required root node property:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) compatible: "syna,as370"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) shall have the following properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Required root node properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) compatible: must contain "marvell,berlin"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) In addition, the above compatible shall be extended with the specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SoC and board used. Currently known SoC compatibles are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) model = "Sony NSZ-GS7";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Marvell Berlin CPU control bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) CPU control register allows various operations on CPUs, like resetting them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) independently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - compatible: should be "marvell,berlin-cpu-ctrl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - reg: address and length of the register set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) cpu-ctrl@f7dd0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) compatible = "marvell,berlin-cpu-ctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) reg = <0xf7dd0000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Marvell Berlin2 chip control binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) Marvell Berlin SoCs have a chip control register set providing several
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) individual registers dealing with pinmux, padmux, clock, reset, and secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) CPU boot address. Unfortunately, the individual registers are spread among the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) chip control registers, so there should be a single DT node only providing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) different functions which are described below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) - compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * the first and second values must be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "simple-mfd", "syscon"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) - reg: address and length of following register sets for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) BG2/BG2CD: chip control register set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) BG2Q: chip control register set and cpu pll registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Marvell Berlin2 system control binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) Marvell Berlin SoCs have a system control register set providing several
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) individual registers dealing with pinmux, padmux, and reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) - compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * the first and second values must be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "simple-mfd", "syscon"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) - reg: address and length of the system control register set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) chip: chip-control@ea0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) compatible = "simple-mfd", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) reg = <0xea0000 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* sub-device nodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) sysctrl: system-controller@d000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) compatible = "simple-mfd", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg = <0xd000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* sub-device nodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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