Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) SP810 System Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) -----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - compatible:	standard compatible string for a Primecell peripheral,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 		see Documentation/devicetree/bindings/arm/primecell.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 		for more details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 		should be: "arm,sp810", "arm,primecell"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - reg:		standard registers property, physical address and size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 		of the control registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - clock-names:	from the common clock bindings, for more details see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		Documentation/devicetree/bindings/clock/clock-bindings.txt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		should be: "refclk", "timclk", "apb_pclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - clocks:	from the common clock bindings, phandle and clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		specifier pairs for the entries of clock-names property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - #clock-cells: from the common clock bindings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		should be: <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - clock-output-names: from the common clock bindings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		should be: "timerclken0", "timerclken1", "timerclken2", "timerclken3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - assigned-clocks: from the common clock binding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		should be: clock specifier for each output clock of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		provider node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - assigned-clock-parents: from the common clock binding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		should be: phandle of input clock listed in clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		property with the highest frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	v2m_sysctl: sysctl@20000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		compatible = "arm,sp810", "arm,primecell";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		reg = <0x020000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		clock-names = "refclk", "timclk", "apb_pclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	};