^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * ARM Snoop Control Unit (SCU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) with a Snoop Control Unit. The register range is usually 256 (0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) References:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Revision r2p0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Revision r0p1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Manial Revision r2p0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - compatible : Should be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "arm,cortex-a9-scu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) "arm,cortex-a5-scu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) "arm,arm11mp-scu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - reg : Specify the base address and the size of the SCU register window.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) scu@a0410000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) compatible = "arm,cortex-a9-scu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) reg = <0xa0410000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };