Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * Copyright (C) 2014, 2016-2017 ARM Limited. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * This program is free software and is provided to you under the terms of the GNU General Public License version 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * A copy of the licence is included with the program, and can also be obtained from Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * ARM Mali-300/400/450 GPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	At least one of these: "arm,mali-300", "arm,mali-400", "arm,mali-450"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	Always: "arm,mali-utgard"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	Mali-450 can also include "arm,mali-400" as it is compatible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	- "arm,mali-400", "arm,mali-utgard" for any Mali-400 GPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	- "arm,mali-450", "arm,mali-400", "arm,mali-utgard" for any Mali-450 GPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	Physical base address and length of the GPU's registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	- List of all Mali interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	- This list must match the number of and the order of entries in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		interrupt-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - interrupt-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	- IRQPP<X> - Name for PP interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	- IRQPPMMU<X> -  Name for interrupts from the PP MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	- IRQPP - Name for the PP broadcast interrupt (Mali-450 only).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	- IRQGP - Name for the GP interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	- IRQGPMMU - Name for the interrupt from the GP MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	- IRQPMU - Name for the PMU interrupt (If pmu is implemented in HW, it must be contained).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - pmu_domain_config:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	- If the Mali internal PMU is present and the PMU IRQ is specified in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		interrupt/interrupt-names ("IRQPMU").This contains the mapping of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		Mali HW units to the PMU power domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	-Mali Dynamic power domain configuration in sequence from 0-11, like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		<GP PP0 PP1 PP2 PP3  PP4 PP5 PP6 PP7 L2$0 L2$1 L2$2>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - pmu-switch-delay:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	- Only needed if the power gates are connected to the PMU in a high fanout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		network. This value is the number of Mali clock cycles it takes to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		enable the power gates and turn on the power mesh. This value will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		have no effect if a daisy chain implementation is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Platform related properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - clocks: Phandle to clock for Mali utgard device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - clock-names: the corresponding names of clock in clocks property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - regulator: Phandle to regulator which is power supplier of mali device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Example for a Mali400_MP1_PMU device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	gpu@12300000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		compatible = "arm,mali-400", "arm,mali-utgard";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		reg = <0x12300000 0x30000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		interrupts = <0 55 4>, <0 56 4>, <0 57 4>, <0 58 4>, <0 59 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPMU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		pmu_domain_config = <0x1 0x4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x2 0x0 0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		pmu_switch_delay = <0xff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		clocks = <clock 122>, <clock 123>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		clock-names = "mali_parent", "mali";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		vdd_g3d-supply = <regulator_Phandle>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }