^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) $id: http://devicetree.org/schemas/arm/l2c2x0.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) title: ARM L2 Cache Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - Rob Herring <robh@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) description: |+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) PL220/PL310 and variants) based level 2 cache controller. All these various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) implementations of the L2 cache controller have compatible programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) models (Note 1). Some of the properties that are just prefixed "cache-*" are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) taken from section 3.7.3 of the Devicetree Specification which can be found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) at:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) https://www.devicetree.org/specifications/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Note 1: The description in this document doesn't apply to integrated L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) integrated L2 controllers are assumed to be all preconfigured by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) early secure boot code. Thus no need to deal with their configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) in the kernel at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) allOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - $ref: /schemas/cache-controller.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - arm,pl310-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - arm,l220-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - arm,l210-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - bcm,bcm11351-a2-pl310-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) # For Broadcom bcm11351 chipset where an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) # offset needs to be added to the address before passing down to the L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) # cache controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - brcm,bcm11351-a2-pl310-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) # Marvell Controller designed to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) # compatible with the ARM one, with system cache mode (meaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) # maintenance operations on L1 are broadcasted to the L2 and L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) # performs the same operation).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - marvell,aurora-system-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) # Marvell Controller designed to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) # compatible with the ARM one with outer cache mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) - marvell,aurora-outer-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) # Marvell Tauros3 cache controller, compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) # with arm,pl310-cache controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - const: marvell,tauros3-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - const: arm,pl310-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) cache-level:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) cache-unified: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) cache-size: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) cache-sets: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) cache-block-size: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) cache-line-size: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) arm,data-latency:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) read, write and setup latencies. Minimum valid values are 1. Controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) without setup latency control should use a value of 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) $ref: /schemas/types.yaml#/definitions/uint32-array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) minItems: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) maxItems: 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) maximum: 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) arm,tag-latency:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) read, write and setup latencies. Controllers without setup latency control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) should use 0. Controllers without separate read and write Tag RAM latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) values should only use the first cell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) $ref: /schemas/types.yaml#/definitions/uint32-array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) minItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) maxItems: 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) maximum: 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) arm,dirty-latency:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) description: Cycles of latency for Dirty RAMs. This is a single cell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) minimum: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) maximum: 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) arm,filter-ranges:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) description: <start length> Starting address and length of window to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) filter. Addresses in the filter window are directed to the M1 port. Other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) addresses will go to the M0 port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) $ref: /schemas/types.yaml#/definitions/uint32-array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) minItems: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) maxItems: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) arm,io-coherent:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) description: indicates that the system is operating in an hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) I/O coherent mode. Valid only when the arm,pl310-cache compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) string is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) # Either a single combined interrupt or up to 9 individual interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) minItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) maxItems: 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) cache-id-part:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) description: cache id part number to be used if it is not present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) on hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) wt-override:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) description: If present then L2 is forced to Write through mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) arm,double-linefill:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) description: Override double linefill enable setting. Enable if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) non-zero, disable if zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) enum: [0, 1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) arm,double-linefill-incr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) description: Override double linefill on INCR read. Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if non-zero, disable if zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) enum: [0, 1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) arm,double-linefill-wrap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) description: Override double linefill on WRAP read. Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if non-zero, disable if zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) enum: [0, 1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) arm,prefetch-drop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) description: Override prefetch drop enable setting. Enable if non-zero,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) disable if zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) enum: [0, 1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) arm,prefetch-offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) description: Override prefetch offset value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) arm,shared-override:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) description: The default behavior of the L220 or PL310 cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) controllers with respect to the shareable attribute is to transform "normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) memory non-cacheable transactions" into "cacheable no allocate" (for reads)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) or "write through no write allocate" (for writes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) On systems where this may cause DMA buffer corruption, this property must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) be specified to indicate that such transforms are precluded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) arm,parity-enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) description: enable parity checking on the L2 cache (L220 or PL310).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) arm,parity-disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) description: disable parity checking on the L2 cache (L220 or PL310).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) marvell,ecc-enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) description: enable ECC protection on the L2 cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) arm,outer-sync-disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) description: disable the outer sync operation on the L2 cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) will randomly hang unless outer sync operations are disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) prefetch-data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) Data prefetch. Value: <0> (forcibly disable), <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) (forcibly enable), property absent (retain settings set by firmware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) enum: [0, 1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) prefetch-instr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) Instruction prefetch. Value: <0> (forcibly disable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) <1> (forcibly enable), property absent (retain settings set by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) firmware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) enum: [0, 1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) arm,dynamic-clock-gating:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) L2 dynamic clock gating. Value: <0> (forcibly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) disable), <1> (forcibly enable), property absent (OS specific behavior,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) preferably retain firmware settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) enum: [0, 1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) arm,standby-mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) description: L2 standby mode enable. Value <0> (forcibly disable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) <1> (forcibly enable), property absent (OS specific behavior,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) preferably retain firmware settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) enum: [0, 1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) arm,early-bresp-disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) description: Disable the CA9 optimization Early BRESP (PL310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) arm,full-line-zero-disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) description: Disable the CA9 optimization Full line of zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) write (PL310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) - cache-unified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) cache-controller@fff12000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) compatible = "arm,pl310-cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) reg = <0xfff12000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) arm,data-latency = <1 1 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) arm,tag-latency = <2 2 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) arm,filter-ranges = <0x80000000 0x8000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) cache-unified;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) cache-level = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) interrupts = <45>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ...
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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