^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Cortina systems Gemini platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) produced by Storlink Semiconductor around 2005. The company was renamed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) later renamed Storm Semiconductor. The chip product name is Storlink SL3516.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) It was derived from earlier products from Storm named SL3316 (Centroid) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) SL3512 (Bulverde).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Storm Semiconductor was acquired by Cortina Systems in 2008 and the SoC was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) produced and used for NAS and similar usecases. In 2014 Cortina Systems was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) in turn acquired by Inphi, who seem to have discontinued this product family.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Many of the IP blocks used in the SoC comes from Faraday Technology.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Required properties (in root node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) compatible = "cortina,gemini";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Required nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - soc: the SoC should be represented by a simple bus encompassing all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) onchip devices, this is referred to as the soc bus node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - syscon: the soc bus node must have a system controller node pointing to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) global control registers, with the compatible string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) "cortina,gemini-syscon", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Required properties on the syscon:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - reg: syscon register location and size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - #clock-cells: should be set to <1> - the system controller is also a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) clock provider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - #reset-cells: should be set to <1> - the system controller is also a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) reset line provider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) The clock sources have shorthand defines in the include file:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) <dt-bindings/clock/cortina,gemini-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) The reset lines have shorthand defines in the include file:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) <dt-bindings/reset/cortina,gemini-reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - timer: the soc bus node must have a timer node pointing to the SoC timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) block, with the compatible string "cortina,gemini-timer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) See: clocksource/cortina,gemini-timer.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - interrupt-controller: the sob bus node must have an interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) node pointing to the SoC interrupt controller block, with the compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) string "cortina,gemini-interrupt-controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) See interrupt-controller/cortina,gemini-interrupt-controller.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) model = "Foo Gemini Machine";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) compatible = "cortina,gemini";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) memory {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) device_type = "memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) reg = <0x00000000 0x8000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) compatible = "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) interrupt-parent = <&intcon>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) syscon: syscon@40000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) compatible = "cortina,gemini-syscon", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) reg = <0x40000000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #reset-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) uart0: serial@42000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) compatible = "ns16550a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) reg = <0x42000000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) resets = <&syscon GEMINI_RESET_UART>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) clocks = <&syscon GEMINI_CLK_UART>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) reg-shift = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) timer@43000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) compatible = "cortina,gemini-timer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) reg = <0x43000000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) interrupt-parent = <&intcon>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) resets = <&syscon GEMINI_RESET_TIMER>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* APB clock or RTC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clocks = <&syscon GEMINI_CLK_APB>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) <&syscon GEMINI_CLK_RTC>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) clock-names = "PCLK", "EXTCLK";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) syscon = <&syscon>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) intcon: interrupt-controller@48000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) compatible = "cortina,gemini-interrupt-controller";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg = <0x48000000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) resets = <&syscon GEMINI_RESET_INTCON0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
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