^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) $id: http://devicetree.org/schemas/arm/cpus.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) title: ARM CPUs bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) description: |+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) The device tree allows to describe the layout of CPUs in a system through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) defining properties for every cpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Bindings for CPU nodes follow the Devicetree Specification, available from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) https://www.devicetree.org/specifications/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) with updates for 32-bit and 64-bit ARM systems provided in this document.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Convention used in this document
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) This document follows the conventions described in the Devicetree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Specification, with the addition:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - square brackets define bitfields, eg reg[7:0] value of the bitfield in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) the reg property contained in bits 7 down to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) =====================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) cpus and cpu node bindings definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) =====================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) The ARM architecture, in accordance with the Devicetree Specification,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) requires the cpus and cpu nodes to be present and contain the properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) described below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Usage and definition depend on ARM architecture version and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) configuration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) On uniprocessor ARM architectures previous to v7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) this property is required and must be set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) On ARM 11 MPcore based systems this property is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) required and matches the CPUID[11:0] register bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) Bits [11:0] in the reg cell must be set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bits [11:0] in CPU ID register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) All other bits in the reg cell must be set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) On 32-bit ARM v7 or later systems this property is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) required and matches the CPU MPIDR[23:0] register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) Bits [23:0] in the reg cell must be set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) bits [23:0] in MPIDR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) All other bits in the reg cell must be set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) On ARM v8 64-bit systems this property is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) and matches the MPIDR_EL1 register affinity bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * If cpus node's #address-cells property is set to 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) The first reg cell bits [7:0] must be set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) bits [39:32] of MPIDR_EL1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) The second reg cell bits [23:0] must be set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bits [23:0] of MPIDR_EL1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * If cpus node's #address-cells property is set to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) The reg cell bits [23:0] must be set to bits [23:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) of MPIDR_EL1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) All other bits in the reg cells must be set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) - arm,arm710t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) - arm,arm720t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) - arm,arm740t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) - arm,arm7ej-s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) - arm,arm7tdmi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) - arm,arm7tdmi-s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) - arm,arm9es
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) - arm,arm9ej-s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) - arm,arm920t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) - arm,arm922t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) - arm,arm925
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) - arm,arm926e-s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) - arm,arm926ej-s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) - arm,arm940t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) - arm,arm946e-s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) - arm,arm966e-s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) - arm,arm968e-s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) - arm,arm9tdmi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) - arm,arm1020e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) - arm,arm1020t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) - arm,arm1022e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) - arm,arm1026ej-s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) - arm,arm1136j-s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) - arm,arm1136jf-s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) - arm,arm1156t2-s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) - arm,arm1156t2f-s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) - arm,arm1176jzf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) - arm,arm1176jz-s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) - arm,arm1176jzf-s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) - arm,arm11mpcore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) - arm,armv8 # Only for s/w models
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) - arm,cortex-a5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) - arm,cortex-a7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) - arm,cortex-a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) - arm,cortex-a9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) - arm,cortex-a12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) - arm,cortex-a15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) - arm,cortex-a17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) - arm,cortex-a32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) - arm,cortex-a34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) - arm,cortex-a35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) - arm,cortex-a53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) - arm,cortex-a55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) - arm,cortex-a57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) - arm,cortex-a65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) - arm,cortex-a72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) - arm,cortex-a73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) - arm,cortex-a75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) - arm,cortex-a76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) - arm,cortex-a77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) - arm,cortex-m0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) - arm,cortex-m0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) - arm,cortex-m1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) - arm,cortex-m3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) - arm,cortex-m4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) - arm,cortex-r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) - arm,cortex-r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) - arm,cortex-r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) - arm,neoverse-e1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) - arm,neoverse-n1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) - brcm,brahma-b15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) - brcm,brahma-b53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) - brcm,vulcan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) - cavium,thunder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) - cavium,thunder2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) - faraday,fa526
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) - intel,sa110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) - intel,sa1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) - marvell,feroceon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) - marvell,mohawk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) - marvell,pj4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) - marvell,pj4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) - marvell,sheeva-v5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) - marvell,sheeva-v7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) - nvidia,tegra132-denver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) - nvidia,tegra186-denver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) - nvidia,tegra194-carmel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) - qcom,krait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) - qcom,kryo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) - qcom,kryo260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) - qcom,kryo280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) - qcom,kryo385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) - qcom,kryo468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) - qcom,kryo485
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) - qcom,scorpion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) enable-method:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) $ref: '/schemas/types.yaml#/definitions/string'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) # On ARM v8 64-bit this property is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) - psci
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) - spin-table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) # On ARM 32-bit systems this property is optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) - actions,s500-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) - allwinner,sun6i-a31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) - allwinner,sun8i-a23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) - allwinner,sun9i-a80-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) - allwinner,sun8i-a83t-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) - amlogic,meson8-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) - amlogic,meson8b-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) - arm,realview-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) - aspeed,ast2600-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) - brcm,bcm11351-cpu-method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) - brcm,bcm23550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) - brcm,bcm2836-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) - brcm,bcm63138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) - brcm,bcm-nsp-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) - brcm,brahma-b15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) - marvell,armada-375-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) - marvell,armada-380-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) - marvell,armada-390-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) - marvell,armada-xp-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) - marvell,98dx3236-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) - marvell,mmp3-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) - mediatek,mt6589-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) - mediatek,mt81xx-tz-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) - qcom,gcc-msm8660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) - qcom,kpss-acc-v1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) - qcom,kpss-acc-v2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) - renesas,apmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) - renesas,r9a06g032-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) - rockchip,rk3036-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) - rockchip,rk3066-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) - socionext,milbeaut-m10v-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) - ste,dbx500-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) - ti,am3352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) - ti,am4372
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) cpu-release-addr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) $ref: '/schemas/types.yaml#/definitions/uint64'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) Required for systems that have an "enable-method"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) property value of "spin-table".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) On ARM v8 64-bit systems must be a two cell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) property identifying a 64-bit zero-initialised
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) memory location.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) cpu-idle-states:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) $ref: '/schemas/types.yaml#/definitions/phandle-array'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) List of phandles to idle state nodes supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) by this cpu (see ./idle-states.yaml).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) capacity-dmips-mhz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) $ref: '/schemas/types.yaml#/definitions/uint32'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 value representing CPU capacity (see ./cpu-capacity.txt) in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) DMIPS/MHz, relative to highest capacity-dmips-mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) in the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dynamic-power-coefficient:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) $ref: '/schemas/types.yaml#/definitions/uint32'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) A u32 value that represents the running time dynamic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) power coefficient in units of uW/MHz/V^2. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) coefficient can either be calculated from power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) measurements or derived by analysis.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) The dynamic power consumption of the CPU is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) proportional to the square of the Voltage (V) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) the clock frequency (f). The coefficient is used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) calculate the dynamic power as below -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) Pdyn = dynamic-power-coefficient * V^2 * f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) where voltage is in V, frequency is in MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) power-domains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) $ref: '/schemas/types.yaml#/definitions/phandle-array'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) List of phandles and PM domain specifiers, as defined by bindings of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PM domain provider (see also ../power_domain.txt).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) power-domain-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) $ref: '/schemas/types.yaml#/definitions/string-array'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) A list of power domain name strings sorted in the same order as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) power-domains property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) For PSCI based platforms, the name corresponding to the index of the PSCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PM domain provider, must be "psci".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) qcom,saw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) $ref: '/schemas/types.yaml#/definitions/phandle'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) Specifies the SAW* node associated with this CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) Required for systems that have an "enable-method" property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * arm/msm/qcom,saw2.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) qcom,acc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) $ref: '/schemas/types.yaml#/definitions/phandle'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) Specifies the ACC* node associated with this CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) Required for systems that have an "enable-method" property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * arm/msm/qcom,kpss-acc.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) rockchip,pmu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) $ref: '/schemas/types.yaml#/definitions/phandle'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) Specifies the syscon node controlling the cpu core power domains.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) Optional for systems that have an "enable-method"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) property value of "rockchip,rk3066-smp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) While optional, it is the preferred way to get access to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) the cpu-core power-domains.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) secondary-boot-reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) $ref: '/schemas/types.yaml#/definitions/uint32'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) Required for systems that have an "enable-method" property value of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) This includes the following SoCs: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) The secondary-boot-reg property is a u32 value that specifies the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) physical address of the register used to request the ROM holding pen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) code release a secondary CPU. The value written to the register is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) formed by encoding the target CPU id into the low bits of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) physical start address it should jump to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) # If the enable-method property contains one of those values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) enable-method:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) - brcm,bcm11351-cpu-method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) - brcm,bcm23550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) - brcm,bcm-nsp-smp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) # and if enable-method is present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) - enable-method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) then:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) - secondary-boot-reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) - device_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dependencies:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) rockchip,pmu: [enable-method]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) additionalProperties: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) compatible = "arm,cortex-a15";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) reg = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) cpu@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) compatible = "arm,cortex-a15";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) reg = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) cpu@100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) compatible = "arm,cortex-a7";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) reg = <0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) cpu@101 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) compatible = "arm,cortex-a7";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) reg = <0x101>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) // Example 2 (Cortex-A8 uniprocessor 32-bit system):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) compatible = "arm,cortex-a8";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) reg = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) compatible = "arm,arm926ej-s";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) reg = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) // Example 4 (ARM Cortex-A57 64-bit system):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) reg = <0x0 0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) enable-method = "spin-table";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) cpu-release-addr = <0 0x20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) cpu@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) reg = <0x0 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) enable-method = "spin-table";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) cpu-release-addr = <0 0x20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) cpu@100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) reg = <0x0 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) enable-method = "spin-table";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) cpu-release-addr = <0 0x20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) cpu@101 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) reg = <0x0 0x101>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) enable-method = "spin-table";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) cpu-release-addr = <0 0x20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) cpu@10000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) reg = <0x0 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) enable-method = "spin-table";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) cpu-release-addr = <0 0x20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) cpu@10001 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) reg = <0x0 0x10001>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) enable-method = "spin-table";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) cpu-release-addr = <0 0x20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) cpu@10100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) reg = <0x0 0x10100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) enable-method = "spin-table";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) cpu-release-addr = <0 0x20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) cpu@10101 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) reg = <0x0 0x10101>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) enable-method = "spin-table";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) cpu-release-addr = <0 0x20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) cpu@100000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) reg = <0x1 0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) enable-method = "spin-table";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) cpu-release-addr = <0 0x20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) cpu@100000001 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) reg = <0x1 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) enable-method = "spin-table";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) cpu-release-addr = <0 0x20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) cpu@100000100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) reg = <0x1 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) enable-method = "spin-table";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) cpu-release-addr = <0 0x20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) cpu@100000101 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) reg = <0x1 0x101>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) enable-method = "spin-table";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) cpu-release-addr = <0 0x20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) cpu@100010000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) reg = <0x1 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) enable-method = "spin-table";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) cpu-release-addr = <0 0x20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) cpu@100010001 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) reg = <0x1 0x10001>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) enable-method = "spin-table";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) cpu-release-addr = <0 0x20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) cpu@100010100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) reg = <0x1 0x10100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) enable-method = "spin-table";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) cpu-release-addr = <0 0x20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) cpu@100010101 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) reg = <0x1 0x10101>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) enable-method = "spin-table";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) cpu-release-addr = <0 0x20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ...
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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