^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) ==========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) ARM CPUs capacity bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ==========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) ==========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) 1 - Introduction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) ==========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) ARM systems may be configured to have cpus with different power/performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) characteristics within the same chip. In this case, additional information has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) to be made available to the kernel for it to be aware of such differences and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) take decisions accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ==========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 2 - CPU capacity definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ==========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) CPU capacity is a number that provides the scheduler information about CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) heterogeneity. Such heterogeneity can come from micro-architectural differences
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) (e.g., ARM big.LITTLE systems) or maximum frequency at which CPUs can run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) (e.g., SMP systems with multiple frequency domains). Heterogeneity in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) context is about differing performance characteristics; this binding tries to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) capture a first-order approximation of the relative performance of CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) CPU capacities are obtained by running a suitable benchmark. This binding makes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) no guarantees on the validity or suitability of any particular benchmark, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) final capacity should, however, be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * A "single-threaded" or CPU affine benchmark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Divided by the running frequency of the CPU executing the benchmark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Not subject to dynamic frequency scaling of the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) For the time being we however advise usage of the Dhrystone benchmark. What
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) above thus becomes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) CPU capacities are obtained by running the Dhrystone benchmark on each CPU at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) max frequency (with caches enabled). The obtained DMIPS score is then divided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) by the frequency (in MHz) at which the benchmark has been run, so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) score obtained in the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ==========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 3 - capacity-dmips-mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ==========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) capacity-dmips-mhz is an optional cpu node [1] property: u32 value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) maximum frequency available to the cpu is then used to calculate the capacity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) value internally used by the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) node, it has to be specified for every other cpu nodes, or the system will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) fall back to the default capacity value for every CPU. If cpufreq is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) available, final capacities are calculated by directly using capacity-dmips-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) mhz values (normalized w.r.t. the highest value found while parsing the DT).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ===========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 4 - Examples
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ===========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) Example 1 (ARM 64-bit, 6-cpu system, two clusters):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) are 1024 and 578 for cluster0 and cluster1. Further normalization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) is done by the operating system based on cluster0@max-freq=1100 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) custer1@max-freq=850, final capacities are 1024 for cluster0 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 446 for cluster1 (576*850/1100).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) cpu-map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) cluster0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) core0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) cpu = <&A57_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) core1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) cpu = <&A57_1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) cluster1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) core0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) cpu = <&A53_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) core1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) cpu = <&A53_1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) core2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) cpu = <&A53_2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) core3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) cpu = <&A53_3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) idle-states {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) entry-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) CPU_SLEEP_0: cpu-sleep-0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) compatible = "arm,idle-state";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) arm,psci-suspend-param = <0x0010000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) local-timer-stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) entry-latency-us = <100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) exit-latency-us = <250>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) min-residency-us = <150>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) CLUSTER_SLEEP_0: cluster-sleep-0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) compatible = "arm,idle-state";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) arm,psci-suspend-param = <0x1010000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) local-timer-stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) entry-latency-us = <800>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) exit-latency-us = <700>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) min-residency-us = <2500>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) A57_0: cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) reg = <0x0 0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) next-level-cache = <&A57_L2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) clocks = <&scpi_dvfs 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) capacity-dmips-mhz = <1024>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) A57_1: cpu@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) compatible = "arm,cortex-a57";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) reg = <0x0 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) next-level-cache = <&A57_L2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) clocks = <&scpi_dvfs 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) capacity-dmips-mhz = <1024>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) A53_0: cpu@100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) compatible = "arm,cortex-a53";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) reg = <0x0 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) next-level-cache = <&A53_L2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) clocks = <&scpi_dvfs 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) capacity-dmips-mhz = <578>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) A53_1: cpu@101 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) compatible = "arm,cortex-a53";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) reg = <0x0 0x101>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) next-level-cache = <&A53_L2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) clocks = <&scpi_dvfs 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) capacity-dmips-mhz = <578>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) A53_2: cpu@102 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) compatible = "arm,cortex-a53";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) reg = <0x0 0x102>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) next-level-cache = <&A53_L2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) clocks = <&scpi_dvfs 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) capacity-dmips-mhz = <578>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) A53_3: cpu@103 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) compatible = "arm,cortex-a53";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) reg = <0x0 0x103>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) enable-method = "psci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) next-level-cache = <&A53_L2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) clocks = <&scpi_dvfs 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) capacity-dmips-mhz = <578>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) A57_L2: l2-cache0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) compatible = "cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) A53_L2: l2-cache1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) compatible = "cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) Example 2 (ARM 32-bit, 4-cpu system, two clusters,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cpus 0,1@1GHz, cpus 2,3@500MHz):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) capacities-dmips-mhz are scaled w.r.t. 2 (cpu@0 and cpu@1), this means that first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) cpu@0 and cpu@1 are twice fast than cpu@2 and cpu@3 (at the same frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) cpu0: cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) compatible = "arm,cortex-a15";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) capacity-dmips-mhz = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) cpu1: cpu@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) compatible = "arm,cortex-a15";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) capacity-dmips-mhz = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) cpu2: cpu@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) compatible = "arm,cortex-a15";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) reg = <0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) capacity-dmips-mhz = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) cpu3: cpu@3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) compatible = "arm,cortex-a15";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) reg = <0x101>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) capacity-dmips-mhz = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ===========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 5 - References
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ===========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) [1] ARM Linux Kernel documentation - CPUs bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) Documentation/devicetree/bindings/arm/cpus.yaml
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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