^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) =======================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) ARM CCI cache coherent interconnect binding description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) =======================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) ARM multi-cluster systems maintain intra-cluster coherency through a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) cache coherent interconnect (CCI) that is capable of monitoring bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) transactions and manage coherency, TLB invalidations and memory barriers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) It allows snooping and distributed virtual memory message broadcast across
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) clusters, through memory mapped interface, with a global control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) space and multiple sets of interface control registers, one per slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * CCI interconnect node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Description: Describes a CCI cache coherent Interconnect component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Node name must be "cci".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Node's parent must be the root node /, and the address space visible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) through the CCI interconnect is the same as the one seen from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) root node (ie from CPUs perspective as per DT standard).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Every CCI node has to define the following properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Value type: <string>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Definition: must contain one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) "arm,cci-400"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) "arm,cci-500"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) "arm,cci-550"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Value type: Integer cells. A register entry, expressed as a pair
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) of cells, containing base and size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Definition: A standard property. Specifies base physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) address of CCI control registers common to all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) interfaces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - ranges:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Value type: Integer cells. An array of range entries, expressed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) as a tuple of cells, containing child address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) parent address and the size of the region in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) child address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Definition: A standard property. Follow rules in the Devicetree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Specification for hierarchical bus addressing. CCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) interfaces addresses refer to the parent node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) addressing scheme to declare their register bases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) CCI interconnect node can define the following child nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - CCI control interface nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Node name must be "slave-if".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) Parent node must be CCI interconnect node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) A CCI control interface node must contain the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) Value type: <string>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) Definition: must be set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "arm,cci-400-ctrl-if"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) - interface-type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) Value type: <string>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) Definition: must be set to one of {"ace", "ace-lite"}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) depending on the interface type the node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) represents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) - reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) Value type: Integer cells. A register entry, expressed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) as a pair of cells, containing base and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) Definition: the base address and size of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) corresponding interface programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) - CCI PMU node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) Parent node must be CCI interconnect node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) A CCI pmu node must contain the following properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) Value type: <string>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) Definition: Must contain one of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "arm,cci-400-pmu,r0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "arm,cci-400-pmu,r1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "arm,cci-400-pmu" - DEPRECATED, permitted only where OS has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) secure access to CCI registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "arm,cci-500-pmu,r0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "arm,cci-550-pmu,r0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) - reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) Value type: Integer cells. A register entry, expressed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) as a pair of cells, containing base and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) Definition: the base address and size of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) corresponding interface programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) - interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) Value type: Integer cells. Array of interrupt specifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) entries, as defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ../interrupt-controller/interrupts.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) Definition: list of counter overflow interrupts, one per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) counter. The interrupts must be specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) starting with the cycle counter overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) interrupt, followed by counter0 overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) interrupt, counter1 overflow interrupt,...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ,counterN overflow interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) The CCI PMU has an interrupt signal for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) counter. The number of interrupts must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) equal to the number of counters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * CCI interconnect bus masters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) Description: masters in the device tree connected to a CCI port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) (inclusive of CPUs and their cpu nodes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) A CCI interconnect bus master node must contain the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) - cci-control-port:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) Value type: <phandle>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) Definition: a phandle containing the CCI control interface node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) the master is connected to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) CPU0: cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) compatible = "arm,cortex-a15";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) cci-control-port = <&cci_control1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) reg = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) CPU1: cpu@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) compatible = "arm,cortex-a15";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) cci-control-port = <&cci_control1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) reg = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) CPU2: cpu@100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) compatible = "arm,cortex-a7";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) cci-control-port = <&cci_control2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) reg = <0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) CPU3: cpu@101 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) compatible = "arm,cortex-a7";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) cci-control-port = <&cci_control2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) reg = <0x101>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dma0: dma@3000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) compatible = "arm,pl330", "arm,primecell";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) cci-control-port = <&cci_control0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) reg = <0x0 0x3000000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) interrupts = <10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #dma-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #dma-channels = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #dma-requests = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) cci@2c090000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) compatible = "arm,cci-400";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) reg = <0x0 0x2c090000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ranges = <0x0 0x0 0x2c090000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) cci_control0: slave-if@1000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) compatible = "arm,cci-400-ctrl-if";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) interface-type = "ace-lite";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) reg = <0x1000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) cci_control1: slave-if@4000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) compatible = "arm,cci-400-ctrl-if";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) interface-type = "ace";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) reg = <0x4000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) cci_control2: slave-if@5000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) compatible = "arm,cci-400-ctrl-if";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) interface-type = "ace";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) reg = <0x5000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pmu@9000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) compatible = "arm,cci-400-pmu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) reg = <0x9000 0x5000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) interrupts = <0 101 4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) <0 102 4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) <0 103 4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) <0 104 4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) <0 105 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) This CCI node corresponds to a CCI component whose control registers sits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) at address 0x000000002c090000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) CCI slave interface @0x000000002c091000 is connected to dma controller dma0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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