^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Atmel system registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Chipid required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: Should be "atmel,sama5d2-chipid"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - reg : Should contain registers location and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) PIT Timer required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - compatible: Should be "atmel,at91sam9260-pit"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - reg: Should contain registers location and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - interrupts: Should contain interrupt for the PIT which is the IRQ line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) shared across all System Controller members.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) PIT64B Timer required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - compatible: Should be "microchip,sam9x60-pit64b"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - reg: Should contain registers location and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - interrupts: Should contain interrupt for PIT64B timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clocks: Should contain the available clock sources for PIT64B timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) System Timer (ST) required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - reg: Should contain registers location and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - interrupts: Should contain interrupt for the ST which is the IRQ line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) shared across all System Controller members.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - clocks: phandle to input clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Its subnodes can be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - watchdog: compatible should be "atmel,at91rm9200-wdt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) RSTC Reset Controller required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - compatible: Should be "atmel,<chip>-rstc".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) <chip> can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) it also can be "microchip,sam9x60-rstc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - reg: Should contain registers location and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - clocks: phandle to input clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) rstc@fffffd00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) compatible = "atmel,at91sam9260-rstc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) reg = <0xfffffd00 0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) clocks = <&clk32k>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) RAMC SDRAM/DDR Controller required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "atmel,at91sam9260-sdramc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "atmel,at91sam9g45-ddramc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "atmel,sama5d3-ddramc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "microchip,sam9x60-ddramc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - reg: Should contain registers location and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ramc0: ramc@ffffe800 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) compatible = "atmel,at91sam9g45-ddramc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) reg = <0xffffe800 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) SHDWC Shutdown Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) - compatible: Should be "atmel,<chip>-shdwc".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) - reg: Should contain registers location and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) - clocks: phandle to input clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) - atmel,wakeup-mode: String, operation mode of the wakeup mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) Supported values are: "none", "high", "low", "any".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) - atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) optional at91sam9260 properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) optional at91sam9rl properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) - atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) optional at91sam9x5 properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) - atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) shdwc@fffffd10 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) compatible = "atmel,at91sam9260-shdwc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) reg = <0xfffffd10 0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) clocks = <&clk32k>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SHDWC SAMA5D2-Compatible Shutdown Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 1) shdwc node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) - compatible: should be "atmel,sama5d2-shdwc" or "microchip,sam9x60-shdwc".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) - reg: should contain registers location and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) - clocks: phandle to input clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) - #address-cells: should be one. The cell is the wake-up input index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) - #size-cells: should be zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) - debounce-delay-us: minimum wake-up inputs debouncer period in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) microseconds. It's usually a board-related property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) - atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) optional microchip,sam9x60-shdwc properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) The node contains child nodes for each wake-up input that the platform uses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 2) input nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) Wake-up input nodes are usually described in the "board" part of the Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) Tree. Note also that input 0 is linked to the wake-up pin and is frequently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) - reg: should contain the wake-up input index [0 - 15].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) - atmel,wakeup-active-high: boolean, the corresponding wake-up input described
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) by the child, forces the wake-up of the core power supply on a high level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) The default is to be active low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) On the SoC side:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) shdwc@f8048010 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) compatible = "atmel,sama5d2-shdwc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) reg = <0xf8048010 0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) clocks = <&clk32k>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) atmel,wakeup-rtc-timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) On the board side:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) shdwc@f8048010 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) debounce-delay-us = <976>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) input@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) input@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) atmel,wakeup-active-high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) Special Function Registers (SFR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) Special Function Registers (SFR) manage specific aspects of the integrated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) memory, bridge implementations, processor and other functionality not controlled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) elsewhere.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) - compatible: Should be "atmel,<chip>-sfr", "syscon" or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "atmel,<chip>-sfrbu", "syscon"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) <chip> can be "sama5d3", "sama5d4" or "sama5d2".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) It also can be "microchip,sam9x60-sfr", "syscon".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) - reg: Should contain registers location and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) sfr@f0038000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) compatible = "atmel,sama5d3-sfr", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) reg = <0xf0038000 0x60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) Security Module (SECUMOD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) The Security Module macrocell provides all necessary secure functions to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) voltage, temperature, frequency and mechanical attacks on the chip. It also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) embeds secure memories that can be scrambled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) The Security Module also offers the PIOBU pins which can be used as GPIO pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) Note that they maintain their voltage during Backup/Self-refresh.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) - compatible: Should be "atmel,<chip>-secumod", "syscon".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) <chip> can be "sama5d2".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) - reg: Should contain registers location and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) - gpio-controller: Marks the port as GPIO controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) - #gpio-cells: There are 2. The pin number is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) first, the second represents additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) parameters such as GPIO_ACTIVE_HIGH/LOW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) secumod@fc040000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) compatible = "atmel,sama5d2-secumod", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) reg = <0xfc040000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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