Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) with a shared L3 memory system, control logic and external interfaces to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) form a multicore cluster. The PMU enables to gather various statistics on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) the operations of the DSU. The PMU provides independent 32bit counters that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) can count any of the supported events, along with a 64bit cycle counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) The PMU is accessed via CPU system registers and has no MMIO component.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) ** DSU PMU required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - compatible	: should be one of :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		"arm,dsu-pmu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - interrupts	: Exactly 1 SPI must be listed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - cpus		: List of phandles for the CPUs connected to this DSU instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ** Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) dsu-pmu-0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	compatible = "arm,dsu-pmu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	cpus = <&cpu_0>, <&cpu_1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };