^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * ARC Performance Counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The ARC700 can be configured with a pipeline performance monitor for counting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) CPU and cache events like cache misses and hits. Like conventional PCT there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) are 100+ hardware conditions dynamically mapped to up to 32 counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Note that:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * The ARC 700 PCT does not support interrupts; although HW events may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) counted, the HW events themselves cannot serve as a trigger for a sample.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - compatible : should contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "snps,arc700-pct"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) pmu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) compatible = "snps,arc700-pct";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };