^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * ARC HS Performance Counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The ARC HS can be configured with a pipeline performance monitor for counting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) CPU and cache events like cache misses and hits. Like conventional PCT there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) are 100+ hardware conditions dynamically mapped to up to 32 counters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) It also supports overflow interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - compatible : should contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) "snps,archs-pct"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) pmu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) compatible = "snps,archs-pct";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };