^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) =====================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) Booting AArch64 Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) =====================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Author: Will Deacon <will.deacon@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Date : 07 September 2012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) This document is based on the ARM booting document by Russell King and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) is relevant to all public releases of the AArch64 Linux kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) The AArch64 exception model is made up of a number of exception levels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) counterpart. EL2 is the hypervisor level and exists only in non-secure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) mode. EL3 is the highest priority level and exists only in secure mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) For the purposes of this document, we will use the term `boot loader`
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) simply to define all software that executes on the CPU(s) before control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) is passed to the Linux kernel. This may include secure monitor and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) hypervisor code, or it may just be a handful of instructions for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) preparing a minimal boot environment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Essentially, the boot loader should provide (as a minimum) the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 1. Setup and initialise the RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 2. Setup the device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 3. Decompress the kernel image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 4. Call the kernel image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 1. Setup and initialise RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ---------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Requirement: MANDATORY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) The boot loader is expected to find and initialise all RAM that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) kernel will use for volatile data storage in the system. It performs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) this in a machine dependent manner. (It may use internal algorithms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) to automatically locate and size all RAM, or it may use knowledge of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) the RAM in the machine, or any other method the boot loader designer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) sees fit.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 2. Setup the device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) -------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) Requirement: MANDATORY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) The device tree blob (dtb) must be placed on an 8-byte boundary and must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) not exceed 2 megabytes in size. Since the dtb will be mapped cacheable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) using blocks of up to 2 megabytes in size, it must not be placed within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) any 2M region which must be mapped with any specific attributes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) NOTE: versions prior to v4.2 also require that the DTB be placed within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) the 512 MB region starting at text_offset bytes below the kernel Image.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 3. Decompress the kernel image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) Requirement: OPTIONAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) The AArch64 kernel does not currently provide a decompressor and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) therefore requires decompression (gzip etc.) to be performed by the boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) loader if a compressed Image target (e.g. Image.gz) is used. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) bootloaders that do not implement this requirement, the uncompressed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) Image target is available instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 4. Call the kernel image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) Requirement: MANDATORY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) The decompressed kernel image contains a 64-byte header as follows::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 code0; /* Executable code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 code1; /* Executable code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u64 text_offset; /* Image load offset, little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u64 image_size; /* Effective Image size, little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u64 flags; /* kernel flags, little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u64 res2 = 0; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u64 res3 = 0; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u64 res4 = 0; /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 magic = 0x644d5241; /* Magic number, little endian, "ARM\x64" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 res5; /* reserved (used for PE COFF offset) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) Header notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) - As of v3.17, all fields are little endian unless stated otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) - code0/code1 are responsible for branching to stext.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) - when booting through EFI, code0/code1 are initially skipped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) res5 is an offset to the PE header and the PE header has the EFI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) entry point (efi_stub_entry). When the stub has done its work, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) jumps to code0 to resume the normal boot process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) - Prior to v3.17, the endianness of text_offset was not specified. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) these cases image_size is zero and text_offset is 0x80000 in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) endianness of the kernel. Where image_size is non-zero image_size is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) little-endian and must be respected. Where image_size is zero,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) text_offset can be assumed to be 0x80000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) - The flags field (introduced in v3.17) is a little-endian 64-bit field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) composed as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ============= ===============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) Bit 0 Kernel endianness. 1 if BE, 0 if LE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) Bit 1-2 Kernel Page size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * 0 - Unspecified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * 1 - 4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * 2 - 16K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * 3 - 64K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) Bit 3 Kernel physical placement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 2MB aligned base should be as close as possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) to the base of DRAM, since memory below it is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) accessible via the linear mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 2MB aligned base may be anywhere in physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) Bits 4-63 Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ============= ===============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) - When image_size is zero, a bootloader should attempt to keep as much
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) memory as possible free for use by the kernel immediately after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) end of the kernel image. The amount of space required will vary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) depending on selected features, and is effectively unbound.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) The Image must be placed text_offset bytes from a 2MB aligned base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) address anywhere in usable system RAM and called there. The region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) between the 2 MB aligned base address and the start of the image has no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) special significance to the kernel, and may be used for other purposes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) At least image_size bytes from the start of the image must be free for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) use by the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) NOTE: versions prior to v4.6 cannot make use of memory below the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) physical offset of the Image so it is recommended that the Image be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) placed as close as possible to the start of system RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) If an initrd/initramfs is passed to the kernel at boot, it must reside
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) entirely within a 1 GB aligned physical memory window of up to 32 GB in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) size that fully covers the kernel Image as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) Any memory described to the kernel (even that below the start of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) image) which is not marked as reserved from the kernel (e.g., with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) memreserve region in the device tree) will be considered as available to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) Before jumping into the kernel, the following conditions must be met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) - Quiesce all DMA capable devices so that memory does not get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) corrupted by bogus network packets or disk data. This will save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) you many hours of debug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) - Primary CPU general-purpose register settings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) - x0 = physical address of device tree blob (dtb) in system RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) - x1 = 0 (reserved for future use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) - x2 = 0 (reserved for future use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) - x3 = 0 (reserved for future use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) - CPU mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) IRQ and FIQ).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) The CPU must be in either EL2 (RECOMMENDED in order to have access to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) the virtualisation extensions) or non-secure EL1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) - Caches, MMUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) The MMU must be off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) The instruction cache may be on or off, and must not hold any stale
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) entries corresponding to the loaded kernel image.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) The address range corresponding to the loaded kernel image must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) cleaned to the PoC. In the presence of a system cache or other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) coherent masters with caches enabled, this will typically require
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) cache maintenance by VA rather than set/way operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) System caches which respect the architected cache maintenance by VA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) operations must be configured and may be enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) System caches which do not respect architected cache maintenance by VA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) operations (not recommended) must be configured and disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) - Architected timers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) CNTFRQ must be programmed with the timer frequency and CNTVOFF must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) be programmed with a consistent value on all CPUs. If entering the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) - Coherency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) All CPUs to be booted by the kernel must be part of the same coherency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) domain on entry to the kernel. This may require IMPLEMENTATION DEFINED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) initialisation to enable the receiving of maintenance operations on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) each CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) - System registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) All writable architected system registers at the exception level where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) the kernel image will be entered must be initialised by software at a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) higher exception level to prevent execution in an UNKNOWN state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) executing on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) - The value of SCR_EL3.FIQ must be the same as the one present at boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) time whenever the kernel is executing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) For systems with a GICv3 interrupt controller to be used in v3 mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) - If EL3 is present:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) all CPUs the kernel is executing on, and must stay constant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) for the lifetime of the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) - If the kernel is entered at EL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) - The DT or ACPI tables must describe a GICv3 interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) For systems with a GICv3 interrupt controller to be used in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) compatibility (v2) mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) - If EL3 is present:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) - If the kernel is entered at EL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) - The DT or ACPI tables must describe a GICv2 interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) For CPUs with pointer authentication functionality:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) - If EL3 is present:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) - SCR_EL3.APK (bit 16) must be initialised to 0b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) - SCR_EL3.API (bit 17) must be initialised to 0b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) - If the kernel is entered at EL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) - HCR_EL2.APK (bit 40) must be initialised to 0b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) - HCR_EL2.API (bit 41) must be initialised to 0b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) For CPUs with Activity Monitors Unit v1 (AMUv1) extension present:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) - If EL3 is present:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) - AMCNTENSET0_EL0 must be initialised to 0b1111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) - AMCNTENSET1_EL0 must be initialised to a platform specific value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) having 0b1 set for the corresponding bit for each of the auxiliary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) counters present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) - If the kernel is entered at EL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) - AMCNTENSET0_EL0 must be initialised to 0b1111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) - AMCNTENSET1_EL0 must be initialised to a platform specific value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) having 0b1 set for the corresponding bit for each of the auxiliary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) counters present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) The requirements described above for CPU mode, caches, MMUs, architected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) timers, coherency and system registers apply to all CPUs. All CPUs must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) enter the kernel in the same exception level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) The boot loader is expected to enter the kernel on each CPU in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) following manner:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) - The primary CPU must jump directly to the first instruction of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) kernel image. The device tree blob passed by this CPU must contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) an 'enable-method' property for each cpu node. The supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) enable-methods are described below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) It is expected that the bootloader will generate these device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) properties and insert them into the blob prior to kernel entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) property in their cpu node. This property identifies a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) naturally-aligned 64-bit zero-initalised memory location.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) These CPUs should spin outside of the kernel in a reserved area of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) memory (communicated to the kernel by a /memreserve/ region in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) device tree) polling their cpu-release-addr location, which must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) contained in the reserved region. A wfe instruction may be inserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) to reduce the overhead of the busy-loop and a sev will be issued by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) the primary CPU. When a read of the location pointed to by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) cpu-release-addr returns a non-zero value, the CPU must jump to this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) value. The value will be written as a single 64-bit little-endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) value, so CPUs must convert the read value to their native endianness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) before jumping to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) - CPUs with a "psci" enable method should remain outside of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) the kernel (i.e. outside of the regions of memory described to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) kernel in the memory node, or in a reserved area of memory described
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) to the kernel by a /memreserve/ region in the device tree). The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) kernel will issue CPU_ON calls as described in ARM document number ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) DEN 0022A ("Power State Coordination Interface System Software on ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) processors") to bring CPUs into the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) The device tree should contain a 'psci' node, as described in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) Documentation/devicetree/bindings/arm/psci.yaml.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) - Secondary CPU general-purpose register settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) - x0 = 0 (reserved for future use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) - x1 = 0 (reserved for future use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) - x2 = 0 (reserved for future use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) - x3 = 0 (reserved for future use)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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