Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) =======================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) S3C24XX CPUfreq support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) =======================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Introduction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) ------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  The S3C24XX series support a number of power saving systems, such as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  the ability to change the core, memory and peripheral operating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  frequencies. The core control is exported via the CPUFreq driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  which has a number of different manual or automatic controls over the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  rate the core is running at.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  There are two forms of the driver depending on the specific CPU and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  how the clocks are arranged. The first implementation used as single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  PLL to feed the ARM, memory and peripherals via a series of dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  and muxes and this is the implementation that is documented here. A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  newer version where there is a separate PLL and clock divider for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  ARM core is available as a separate driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  The code core manages the CPU specific drivers, any data that they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  need to register and the interface to the generic drivers/cpufreq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  system. Each CPU registers a driver to control the PLL, clock dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  and anything else associated with it. Any board that wants to use this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  framework needs to supply at least basic details of what is required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  The core registers with drivers/cpufreq at init time if all the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  necessary has been supplied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) CPU support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  The support for each CPU depends on the facilities provided by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  SoC and the driver as each device has different PLL and clock chains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  associated with it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Slow Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ---------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)  The SLOW mode where the PLL is turned off altogether and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)  system is fed by the external crystal input is currently not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)  supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) sysfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) -----
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)  The core code exports extra information via sysfs in the directory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)  devices/system/cpu/cpu0/arch-freq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) Board Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) -------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)  Each board that wants to use the cpufreq code must register some basic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)  information with the core driver to provide information about what the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)  board requires and any restrictions being placed on it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)  The board needs to supply information about whether it needs the IO bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)  timings changing, any maximum frequency limits and information about the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)  SDRAM refresh rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) Document Author
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ---------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) Ben Dooks, Copyright 2009 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) Licensed under GPLv2