^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) ==============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) MFP Configuration for PXA2xx/PXA3xx Processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ==============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Eric Miao <eric.miao@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) later PXA series processors. This document describes the existing MFP API,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) and how board/platform driver authors could make use of it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Basic Concept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) =============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Unlike the GPIO alternate function settings on PXA25x and PXA27x, a new MFP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) mechanism is introduced from PXA3xx to completely move the pin-mux functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) out of the GPIO controller. In addition to pin-mux configurations, the MFP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) also controls the low power state, driving strength, pull-up/down and event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) detection of each pin. Below is a diagram of internal connections between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) the MFP logic and the remaining SoC peripherals::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) +--------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) | |--(GPIO19)--+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) | GPIO | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) | |--(GPIO...) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) +--------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) | +---------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) +--------+ +------>| |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) | PWM2 |--(PWM_OUT)-------->| MFP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) +--------+ +------>| |-------> to external PAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) | +---->| |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) +--------+ | | +-->| |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) | SSP2 |---(TXD)----+ | | +---------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) +--------+ | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) +--------+ | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) | Keypad |--(MKOUT4)----+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) +--------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) +--------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) | UART2 |---(TXD)--------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) +--------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) NOTE: the external pad is named as MFP_PIN_GPIO19, it doesn't necessarily
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mean it's dedicated for GPIO19, only as a hint that internally this pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) can be routed from GPIO19 of the GPIO controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) To better understand the change from PXA25x/PXA27x GPIO alternate function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) to this new MFP mechanism, here are several key points:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 1. GPIO controller on PXA3xx is now a dedicated controller, same as other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) internal controllers like PWM, SSP and UART, with 128 internal signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) which can be routed to external through one or more MFPs (e.g. GPIO<0>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) can be routed through either MFP_PIN_GPIO0 as well as MFP_PIN_GPIO0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) see arch/arm/mach-pxa/mfp-pxa300.h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 2. Alternate function configuration is removed from this GPIO controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) the remaining functions are pure GPIO-specific, i.e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) - GPIO signal level control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) - GPIO direction control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) - GPIO level change detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 3. Low power state for each pin is now controlled by MFP, this means the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PGSRx registers on PXA2xx are now useless on PXA3xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 4. Wakeup detection is now controlled by MFP, PWER does not control the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) wakeup from GPIO(s) any more, depending on the sleeping state, ADxER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) (as defined in pxa3xx-regs.h) controls the wakeup from MFP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) NOTE: with such a clear separation of MFP and GPIO, by GPIO<xx> we normally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mean it is a GPIO signal, and by MFP<xxx> or pin xxx, we mean a physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pad (or ball).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MFP API Usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) =============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) For board code writers, here are some guidelines:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 1. include ONE of the following header files in your <board>.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) - #include "mfp-pxa25x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) - #include "mfp-pxa27x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) - #include "mfp-pxa300.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) - #include "mfp-pxa320.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) - #include "mfp-pxa930.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) NOTE: only one file in your <board>.c, depending on the processors used,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) because pin configuration definitions may conflict in these file (i.e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) same name, different meaning and settings on different processors). E.g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) for zylonite platform, which support both PXA300/PXA310 and PXA320, two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) separate files are introduced: zylonite_pxa300.c and zylonite_pxa320.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) (in addition to handle MFP configuration differences, they also handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) the other differences between the two combinations).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) NOTE: PXA300 and PXA310 are almost identical in pin configurations (with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PXA310 supporting some additional ones), thus the difference is actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) covered in a single mfp-pxa300.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 2. prepare an array for the initial pin configurations, e.g.::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static unsigned long mainstone_pin_config[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Chip Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) GPIO15_nCS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* LCD - 16bpp Active TFT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) GPIOxx_TFT_LCD_16BPP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) GPIO16_PWM0_OUT, /* Backlight */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) GPIO32_MMC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) GPIO112_MMC_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) GPIO92_MMC_DAT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) GPIO109_MMC_DAT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) GPIO110_MMC_DAT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) GPIO111_MMC_DAT_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) a) once the pin configurations are passed to pxa{2xx,3xx}_mfp_config(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) and written to the actual registers, they are useless and may discard,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) adding '__initdata' will help save some additional bytes here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) b) when there is only one possible pin configurations for a component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) some simplified definitions can be used, e.g. GPIOxx_TFT_LCD_16BPP on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PXA25x and PXA27x processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) c) if by board design, a pin can be configured to wake up the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) from low power state, it can be 'OR'ed with any of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) WAKEUP_ON_EDGE_BOTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) WAKEUP_ON_EDGE_RISE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) WAKEUP_ON_EDGE_FALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) WAKEUP_ON_LEVEL_HIGH - specifically for enabling of keypad GPIOs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) to indicate that this pin has the capability of wake-up the system,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) and on which edge(s). This, however, doesn't necessarily mean the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pin _will_ wakeup the system, it will only when set_irq_wake() is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) invoked with the corresponding GPIO IRQ (GPIO_IRQ(xx) or gpio_to_irq())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) and eventually calls gpio_set_wake() for the actual register setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) d) although PXA3xx MFP supports edge detection on each pin, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) internal logic will only wakeup the system when those specific bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) in ADxER registers are set, which can be well mapped to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) corresponding peripheral, thus set_irq_wake() can be called with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) the peripheral IRQ to enable the wakeup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MFP on PXA3xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) =============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) Every external I/O pad on PXA3xx (excluding those for special purpose) has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) one MFP logic associated, and is controlled by one MFP register (MFPR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) The MFPR has the following bit definitions (for PXA300/PXA310/PXA320)::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) +-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) | RESERVED |PS|PU|PD| DRIVE |SS|SD|SO|EC|EF|ER|--| AF_SEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) +-------------------------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) Bit 3: RESERVED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) Bit 4: EDGE_RISE_EN - enable detection of rising edge on this pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) Bit 5: EDGE_FALL_EN - enable detection of falling edge on this pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) Bit 6: EDGE_CLEAR - disable edge detection on this pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) Bit 7: SLEEP_OE_N - enable outputs during low power modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) Bit 8: SLEEP_DATA - output data on the pin during low power modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) Bit 9: SLEEP_SEL - selection control for low power modes signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) Bit 13: PULLDOWN_EN - enable the internal pull-down resistor on this pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) Bit 14: PULLUP_EN - enable the internal pull-up resistor on this pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) Bit 15: PULL_SEL - pull state controlled by selected alternate function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) (0) or by PULL{UP,DOWN}_EN bits (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) Bit 0 - 2: AF_SEL - alternate function selection, 8 possibilities, from 0-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) Bit 10-12: DRIVE - drive strength and slew rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 0b000 - fast 1mA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 0b001 - fast 2mA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 0b002 - fast 3mA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 0b003 - fast 4mA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 0b004 - slow 6mA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 0b005 - fast 6mA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 0b006 - slow 10mA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 0b007 - fast 10mA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MFP Design for PXA2xx/PXA3xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) Due to the difference of pin-mux handling between PXA2xx and PXA3xx, a unified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MFP API is introduced to cover both series of processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) The basic idea of this design is to introduce definitions for all possible pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) configurations, these definitions are processor and platform independent, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) the actual API invoked to convert these definitions into register settings and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) make them effective there-after.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) Files Involved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) --------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) - arch/arm/mach-pxa/include/mach/mfp.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 1. Unified pin definitions - enum constants for all configurable pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 2. processor-neutral bit definitions for a possible MFP configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) - arch/arm/mach-pxa/mfp-pxa3xx.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) for PXA3xx specific MFPR register bit definitions and PXA3xx common pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) - arch/arm/mach-pxa/mfp-pxa2xx.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) for PXA2xx specific definitions and PXA25x/PXA27x common pin configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) - arch/arm/mach-pxa/mfp-pxa25x.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) arch/arm/mach-pxa/mfp-pxa27x.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) arch/arm/mach-pxa/mfp-pxa300.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) arch/arm/mach-pxa/mfp-pxa320.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) arch/arm/mach-pxa/mfp-pxa930.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) for processor specific definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) - arch/arm/mach-pxa/mfp-pxa3xx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) - arch/arm/mach-pxa/mfp-pxa2xx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) for implementation of the pin configuration to take effect for the actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) Pin Configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) -----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) The following comments are copied from mfp.h (see the actual source code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) for most updated info)::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * a possible MFP configuration is represented by a 32-bit integer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * bit 10..12 - Alternate Function Selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * bit 13..15 - Drive Strength
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * bit 16..18 - Low Power Mode State
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * bit 19..20 - Low Power Mode Edge Detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * bit 21..22 - Run Mode Pull State
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * to facilitate the definition, the following macros are provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * MFP_CFG_DEFAULT - default MFP configuration value, with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * alternate function = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * drive strength = fast 3mA (MFP_DS03X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * low power mode = default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * edge detection = none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * MFP_CFG - default MFPR value with alternate function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * MFP_CFG_DRV - default MFPR value with alternate function and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * pin drive strength
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * MFP_CFG_LPM - default MFPR value with alternate function and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * low power mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * MFP_CFG_X - default MFPR value with alternate function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * pin drive strength and low power mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) Examples of pin configurations are::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) which reads GPIO94 can be configured as SSP3_RXD, with alternate function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) selection of 1, driving strength of 0b101, and a float state in low power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) NOTE: this is the default setting of this pin being configured as SSP3_RXD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) which can be modified a bit in board code, though it is not recommended to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) do so, simply because this default setting is usually carefully encoded,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) and is supposed to work in most cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) Register Settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) -----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) Register settings on PXA3xx for a pin configuration is actually very
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) straight-forward, most bits can be converted directly into MFPR value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) in a easier way. Two sets of MFPR values are calculated: the run-time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ones and the low power mode ones, to allow different settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) The conversion from a generic pin configuration to the actual register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) settings on PXA2xx is a bit complicated: many registers are involved,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) including GAFRx, GPDRx, PGSRx, PWER, PKWR, PFER and PRER. Please see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mfp-pxa2xx.c for how the conversion is made.
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags