^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) =============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) Current State
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) =============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) The following describes the current state of the NetWinder's floating point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) emulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) In the following nomenclature is used to describe the floating point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) instructions. It follows the conventions in the ARM manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) ::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) <S|D|E> = <single|double|extended>, no default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) {P|M|Z} = {round to +infinity,round to -infinity,round to zero},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) default = round to nearest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Note: items enclosed in {} are optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Floating Point Coprocessor Data Transfer Instructions (CPDT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) LDF/STF - load and store floating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) <LDF|STF>{cond}<S|D|E> Fd, Rn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) <LDF|STF>{cond}<S|D|E> Fd, [Rn, #<expression>]{!}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) <LDF|STF>{cond}<S|D|E> Fd, [Rn], #<expression>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) These instructions are fully implemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) LFM/SFM - load and store multiple floating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Form 1 syntax:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) <LFM|SFM>{cond}<S|D|E> Fd, <count>, [Rn]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) <LFM|SFM>{cond}<S|D|E> Fd, <count>, [Rn, #<expression>]{!}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) <LFM|SFM>{cond}<S|D|E> Fd, <count>, [Rn], #<expression>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Form 2 syntax:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) <LFM|SFM>{cond}<FD,EA> Fd, <count>, [Rn]{!}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) These instructions are fully implemented. They store/load three words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) for each floating point register into the memory location given in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) instruction. The format in memory is unlikely to be compatible with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) other implementations, in particular the actual hardware. Specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mention of this is made in the ARM manuals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Floating Point Coprocessor Register Transfer Instructions (CPRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Conversions, read/write status/control register instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FLT{cond}<S,D,E>{P,M,Z} Fn, Rd Convert integer to floating point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) FIX{cond}{P,M,Z} Rd, Fn Convert floating point to integer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) WFS{cond} Rd Write floating point status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) RFS{cond} Rd Read floating point status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) WFC{cond} Rd Write floating point control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) RFC{cond} Rd Read floating point control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) FLT/FIX are fully implemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) RFS/WFS are fully implemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) RFC/WFC are fully implemented. RFC/WFC are supervisor only instructions, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) presently check the CPU mode, and do an invalid instruction trap if not called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) from supervisor mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) Compare instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) CMF{cond} Fn, Fm Compare floating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) CMFE{cond} Fn, Fm Compare floating with exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) CNF{cond} Fn, Fm Compare negated floating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) CNFE{cond} Fn, Fm Compare negated floating with exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) These are fully implemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) Floating Point Coprocessor Data Instructions (CPDT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ---------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) Dyadic operations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ADF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - add
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) SUF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - subtract
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) RSF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse subtract
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MUF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - multiply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) DVF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - divide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) RDV{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse divide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) These are fully implemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) FML{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - fast multiply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) FDV{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - fast divide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) FRD{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - fast reverse divide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) These are fully implemented as well. They use the same algorithm as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) non-fast versions. Hence, in this implementation their performance is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) equivalent to the MUF/DVF/RDV instructions. This is acceptable according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) to the ARM manual. The manual notes these are defined only for single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) operands, on the actual FPA11 hardware they do not work for double or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) extended precision operands. The emulator currently does not check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) the requested permissions conditions, and performs the requested operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) RMF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - IEEE remainder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) This is fully implemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) Monadic operations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MVF{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - move
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MNF{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - move negated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) These are fully implemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ABS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - absolute value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SQT{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - square root
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) RND{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - round
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) These are fully implemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) URD{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - unnormalized round
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) NRM{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - normalize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) These are implemented. URD is implemented using the same code as the RND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) instruction. Since URD cannot return a unnormalized number, NRM becomes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) a NOP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) Library calls:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) POW{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) RPW{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) POL{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - polar angle (arctan2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) LOG{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - logarithm to base 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) LGN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - logarithm to base e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) EXP{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - exponent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) SIN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - sine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) COS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - cosine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) TAN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - tangent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ASN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arcsine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ACS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arccosine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ATN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arctangent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) These are not implemented. They are not currently issued by the compiler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) and are handled by routines in libc. These are not implemented by the FPA11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) hardware, but are handled by the floating point support code. They should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) be implemented in future versions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) Signalling:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) Signals are implemented. However current ELF kernels produced by Rebel.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) have a bug in them that prevents the module from generating a SIGFPE. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) is caused by a failure to alias fp_current to the kernel variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) current_set[0] correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) The kernel provided with this distribution (vmlinux-nwfpe-0.93) contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) a fix for this problem and also incorporates the current version of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) emulator directly. It is possible to run with no floating point module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) loaded with this kernel. It is provided as a demonstration of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) technology and for those who want to do floating point work that depends
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) on signals. It is not strictly necessary to use the module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) A module (either the one provided by Russell King, or the one in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) distribution) can be loaded to replace the functionality of the emulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) built into the kernel.
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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