^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) .. SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) =================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) PCI Test Function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) =================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) :Author: Kishon Vijay Abraham I <kishon@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Traditionally PCI RC has always been validated by using standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) However with the addition of EP-core in linux kernel, it is possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) to configure a PCI controller that can operate in EP mode to work as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) a test device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) The PCI endpoint test device is a virtual device (defined in software)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) used to test the endpoint functionality and serve as a sample driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) for other PCI endpoint devices (to use the EP framework).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) The PCI endpoint test device has the following registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 1) PCI_ENDPOINT_TEST_MAGIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 2) PCI_ENDPOINT_TEST_COMMAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 3) PCI_ENDPOINT_TEST_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 4) PCI_ENDPOINT_TEST_SRC_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 5) PCI_ENDPOINT_TEST_DST_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 6) PCI_ENDPOINT_TEST_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 7) PCI_ENDPOINT_TEST_CHECKSUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 8) PCI_ENDPOINT_TEST_IRQ_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 9) PCI_ENDPOINT_TEST_IRQ_NUMBER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * PCI_ENDPOINT_TEST_MAGIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) This register will be used to test BAR0. A known pattern will be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) and read back from MAGIC register to verify BAR0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * PCI_ENDPOINT_TEST_COMMAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) This register will be used by the host driver to indicate the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) that the endpoint device must perform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ======== ================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Bitfield Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ======== ================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Bit 0 raise legacy IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Bit 1 raise MSI IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Bit 2 raise MSI-X IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Bit 3 read command (read data from RC buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) Bit 4 write command (write data to RC buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Bit 5 copy command (copy data from one RC buffer to another RC buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ======== ================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * PCI_ENDPOINT_TEST_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) This register reflects the status of the PCI endpoint device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ======== ==============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) Bitfield Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ======== ==============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) Bit 0 read success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) Bit 1 read fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) Bit 2 write success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) Bit 3 write fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) Bit 4 copy success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) Bit 5 copy fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) Bit 6 IRQ raised
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) Bit 7 source address is invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) Bit 8 destination address is invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ======== ==============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * PCI_ENDPOINT_TEST_SRC_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) This register contains the source address (RC buffer address) for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) COPY/READ command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * PCI_ENDPOINT_TEST_DST_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) This register contains the destination address (RC buffer address) for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) the COPY/WRITE command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * PCI_ENDPOINT_TEST_IRQ_TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) This register contains the interrupt type (Legacy/MSI) triggered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) Possible types:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ====== ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) Legacy 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MSI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MSI-X 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ====== ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * PCI_ENDPOINT_TEST_IRQ_NUMBER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) This register contains the triggered ID interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) Admissible values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ====== ===========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) Legacy 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MSI [1 .. 32]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MSI-X [1 .. 2048]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ====== ===========
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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