^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) What: /sys/devices/*/<our-device>/fuse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) Date: February 2014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Contact: Peter De Schrijver <pdeschrijver@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Description: read-only access to the efuses on Tegra20, Tegra30, Tegra114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) and Tegra124 SoC's from NVIDIA. The efuses contain write once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) data programmed at the factory. The data is layed out in 32bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) words in LSB first format. Each bit represents a single value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) as decoded from the fuse registers. Bits order/assignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) exactly matches the HW registers, including any unused bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Users: any user space application which wants to read the efuses on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Tegra SoC's