Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) What:		/sys/kernel/debug/moxtet/input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) Date:		March 2019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) KernelVersion:	5.3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Contact:	Marek Behún <marek.behun@nic.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Description:	(Read) Read input from the shift registers, in hexadecimal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 		Returns N+1 bytes, where N is the number of Moxtet connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 		modules. The first byte is from the CPU board itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 		Example::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 			101214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 		==  =======================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		10  CPU board with SD card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		12  2 = PCIe module, 1 = IRQ not active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		14  4 = Peridot module, 1 = IRQ not active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		==  =======================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) What:		/sys/kernel/debug/moxtet/output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Date:		March 2019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) KernelVersion:	5.3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Contact:	Marek Behún <marek.behun@nic.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Description:	(RW) Read last written value to the shift registers, in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		hexadecimal, or write values to the shift registers, also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		in hexadecimal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		Example::
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		    0102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		==  ================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		01  01 was last written, or is to be written, to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		    first module's shift register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		02  the same for second module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		==  ================================================